ADE7518
Table 106. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
7
6
Mnemonic
RXFLAG
VSWSOURCE
Default
0
1
Description
If this bit is set, indicates that an Rx edge event triggered wake-up from PSM2.
Indicates the power supply that is connected internally to V SWOUT . If this bit is set, V SWOUT =
V DD . If this bit is cleared, V SWOUT = V BAT .
5
4
3
2
1 to 0
VDD_OK
PLL_FLT
REF_BAT_EN
Reserved
RXPROG[1:0]
1
0
0
0
00
If this bit is set, indicates that V DD power supply is acceptable for operation.
If this bit is set, indicates that PLL is not locked.
If this bit is set, the internal voltage reference is enabled in PSM2 mode.
This bit should be kept to zero.
Controls the function of the P1.0/RxD pin.
RXPROG[1:0] Result
00 GPIO
01
11
Table 107. Start ADC Measurement SFR (ADCGO, 0xD8)
Rx with wake-up disabled
Rx with wake-up enabled
Bit
7
Address
0xDF
Mnemonic
PLL_FTL_ACK
Default
0
Description
Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault
is generated if a reset was caused because the PLL lost lock.
6 to 0
0xDE to 0xD8
Reserved
0
Reserved.
Rev. 0 | Page 99 of 128
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